See the original posting on Anandtech
In the eternal battle to drive more details out of AMD ahead of the full launch of its new Zen microarchitecture based CPUs, today AMD is lifting the lid on some new features in order to whet the appetite (and appease the hype-train, perhaps) and that will be part of the product launch. We now have new details on the brand naming, some platform details, and a high-level overview of what will be the key points being promoted when it comes to market.
We’ve covered a lot of Zen, from the initial announcement to some of the microarchitecture details at Hot Chips through to discussing the utility of singular benchmark data and then what might be happening on the server side through a detailed analysis of motherboards on display. A lot of us want it out already, and when it does, it will come out under the brand ‘Ryzen’.
Ryzen and AM4
It is pronounced ‘Rye-zen’, not ‘Riz-zen’, to clarify.
As expected, there will be several SKUs in the brand, although AMD is not releasing many details aside from the cache arrangement of the 8-core, thread chip (which we already knew was 4MB of L2 + [8+8] MB of L3 victim-cache), and that the base clock for the high-end SKU will be at least 3.4+ GHz. The fact that AMD says ‘at least’ dictates that they are still deciding exactly what to do here, although a similar thing was said leading up to the launch of Polaris-based RX cards (though that’s a different department).
We know that Ryzen will use the AM4 platform, shared with the previous generation Bristol Ridge which remains an OEM-only product for now. We’ve gone into detail about how AM4 will operate, using a split IO design between the CPU and the chipset such that for minimal function, a chipset is not needed, however AMD has pointed out that with Ryzen, AM4 with the right chipset will support USB 3.1 Gen 2 (10 Gbps), NVMe SSDs, SATA-Express, and offer ‘ultimate upgradability’. The latter point may give an indication to the Ryzen based chipsets might offer numerous PCIe lanes, similar to what Intel does on the 100-series. That said, Intel has been developing that feature over years, and the Bristol Ridge chipsets for AM4 that have been announced already are not quite up to par with that, so it will be interesting to see.
We’re still waiting for detailed information on PCIe lane counts on Ryzen, how big that micro-op cache is in the core, if the L3 victim cache has limitations, how good the DDR4 controller is, power consumption, and what exactly the single core performance / IPC level is. Actually AMD did go into more detail with a few of these areas as well.
Power, Performance and Pre-Fetch: AMD SenseMI
Part of the demo in the pre-brief was a Handbrake video transcode, a multithreaded test, showing a near-identical completion time between a high-frequency Ryzen without turbo compared to an i7-6900K at similar frequencies. This mirrors the Blender test we saw back in August, although using a new benchmark this time but still multi-threaded. AMD also fired up some power meters, showing that Ryzen power consumption in this test was a few watts lower than the Intel part, implying that AMD is meeting its targets for power, performance and as a result, efficiency. The 40%+ improvement in IPC/efficiency is still being thrown around, and AMD seems confident that this target has been surpassed.
To that extent, at the pre-briefing, Ryan was shown two systems running Titan X graphics cards in SLI and Battlefield 1 at 4K settings – one system was running Ryzen, and the other an i7-6900K (the 8-core Broadwell-E chip). Ryan was unable to determine an obvious visual difference between the two frame-rate wise, which was the point of the demo.
Mark Papermaster, CTO of AMD, explained during our briefing that during the Zen design stages, up to 300 engineers were working on the core engine with an aggressive mantra of higher IPC for no power gain. This is not an uncommon strategy for core designs. Part of this will be down to two new power modes, that adjust and extend the power/frequency curve, which are part of AMD’s new 5-stage ‘SenseMI’ technology.
SenseMI Stage 1: Pure Power
A number of recent microprocessor launches have revolved around silicon-optimized power profiles. We are now removed from the ‘one DVFS curve fits all’ application for high-end silicon, and AMD’s solution in Ryzen will be called Pure Power. The short explanation is that using distributed embedded sensors in the design (first introduced in bulk with Carrizo) that monitor temperature, speed and voltage, and the control center can manage the power consumption in real time. The glue behind this technology comes in form of AMD’s new ‘Infinity Fabric’.
‘What is this new Infinity Fabric?’ I hear you say. It was only explained in the context of that it provides control and through the Infinity System Management Unit it can adjust power consumption while keeping in mind everything else that’s happening. The fact that it’s described as a fabric suggests that it goes through the entire processor, connecting various parts together as part of that control. Whether this is something wildly different to what we saw in Carrizo, aside from being the next-gen power adjustment and under a new name, is hard to determine at this point but we are probing for more details.
The upshot of Pure Power is that the DVFS curve is lower and more optimized for a given piece of silicon than a generic DVFS curve, which results in giving lower power at various/all levels of performance. This in turn benefits the next part of SenseMI, Precision Boost.
SenseMi Stage 2: Precision Boost
For almost a decade now, most commercial PC processors have invoked some form of boost technology to enable processors to use less power when idle and fully take advantage of the power budget when only a few elements of the core design is needed. We see processors that sit at 2.2 GHz that boost to 2.7 GHz when only one thread is needed, for example, because the whole chip still remains under the power limit. AMD is implementing Precision Boost for Ryzen, increasing the DVFS curve to better performance due to Pure Power, but also offering frequency jumps in 25 MHz steps which is new.